DSP Architecture for Efficient DSP Core Processing

The demand for high-performance computing, particularly in areas such as artificial intelligence (AI), machine learning (ML), 5G communications, radar, and advanced sensors, is driving a relentless pursuit of greater compute efficiency in military and aerospace applications.

Traditional architectures, while powerful, often face limitations in power consumption and latency for real-time, high-throughput signal processing. AMD’s Versal™ Adaptive SoCs, with their revolutionary heterogeneous architecture, represent a paradigm shift, especially in how they harness new Digital Signal Processing (DSP) architectures and optimized core processing for unparalleled compute efficiency.

At the heart of Versal ASoCs compute prowess lies a blend of specialized processing engines:

• Scalar Engines (Arm CPUs)
• Adaptable Engines (programmable logic, i.e., FPGA fabric)
• Intelligent Engines (AI Engines and dedicated DSP blocks)

This heterogeneous approach allows designers to precisely match workloads to the most efficient compute resource, a critical factor in achieving optimal performance per watt.

What Is the Purpose of DSP?

At its core, Digital Signal Processing (DSP) converts and manipulates signals to extract meaningful information in real time. This makes DSP architecture fundamental to tasks such as noise reduction, radar signal analysis, and secure communications. AMD Versal Adaptive SoCs expand on this foundation with advanced DSP core processing blocks and AI Engines that deliver unprecedented efficiency.

The Evolution of DSP in AMD Versal

Traditional FPGAs have long been a go-to for DSP acceleration due to their inherent parallelism. Their configurable logic blocks (CLBs) and dedicated DSP slices (like the DSP48E2 in UltraScale+) enable highly parallel and low-latency implementations of digital filters, FFTs, and other signal processing algorithms. However, as DSP demands escalate into the teramacs-per-second range with stricter power budgets, even these highly optimized blocks can face limitations in density and power efficiency when scaled.

Versal addresses this by evolving its DSP architecture via two key mechanisms. The DSP58 block is the sixth generation of AMD’s dedicated DSP slices within the programmable logic. Building on the robust DSP48E2, the DSP58 offers significant enhancements, such as wider multipliers, native INT8 (8-bit integer) vector dot products, and efficient 18×18 complex multiplication. This avoids the need for resource-intensive soft implementations in programmable logic, leading to substantial area and power savings. Further, DSP58 can now perform single-precision floating point multiplication, offering more flexibility for algorithms.

FPGA DSP Acceleration with AI Engines

Versal’s revolutionary AI engines is an area where this generation of ASoCs truly differentiates itself for compute efficiency in DSP. The AI Engines are an array of highly optimized, VLIW/SIMD vector processors. While named for AI, their architecture makes them exceptionally well-suited for high-throughput, deterministic, and power-efficient digital signal processing. The AI engines can simultaneously perform tasks like:

• Mathematical operations
• Memory loads
• Memory stores within the same clock cycle, maximizing data flow and compute utilization

Advancements in DSP Core Processing with DSP58

The synergy between the enhanced DSP58 blocks and the AI Engines, orchestrated by the programmable Network-on-Chip (NoC), is key to Versal’s compute efficiency. FPGA designers can strategically partition DSP workloads via the Vivado Design Suite. High-throughput, highly parallel, and deterministic vector operations (like FIR filters, FFTs, polyphase channelizers, beamforming) are ideally suited for the AI Engines. More complex, control-oriented, or irregular DSP functions can leverage the flexibility of the DSP58 blocks within the programmable logic. Scalar control and overall system management are handled by the Arm CPUs in the Processing System. Workload partitioning, data flow optimization, and implementing core DSP functions in hard IP (DSP58 and AI Engines) allows designers to free up valuable programmable logic resources for other workloads providing unparalleled compute efficiency.

Defining the Purpose of DSP in Versal

In conclusion, AMD Versal Adaptive SoCs redefine compute efficiency by integrating a new DSP architectures that include both highly optimized DSP58 blocks within the programmable logic and a scalable array of AI Engines. By combining a unified software platform with an intelligent interconnect, the heterogeneous architecture enables designers to map DSP workloads in Vivado to the most power- and area-efficient resources. The result is a platform that delivers unprecedented performance per watt, enabling a new generation of intelligent, real-time, and high-throughput applications across a multitude of industries.

Do you have questions about how to implement your instantiation of firmware on an AMD Versal™ based ASoC solution? Contact New Wave Design to discuss your requirements and learn more about the Versal family of ASoCs or use of the Vivado Design Suite.