Technical Hurdles in Migrating to Versal™: What Engineers Need to Know

AMD’s Versal™ family unlocks advanced capabilities for FPGA applications, but migration from UltraScale/UltraScale+ can feel like stepping into an entirely new — and challenging — architectural landscape.

Successfully navigating the transition requires a clear understanding of the technical challenges ahead, allowing engineers to plan a smooth migration. Here’s what you need to know.

Versal Code Portability and Hardware Changes

Code is the “secret sauce,” while the hardware platform serves to execute code and showcase its capabilities. Migrating from UltraScale/UltraScale+ to Versal introduces code portability challenges, as some blocks won’t automatically map to the new architecture. For example:

• Intrachip routing and AXI buses might require special resources for clocking, transceivers, and I/O mapping
• HDL might need to be rewritten to match Versal interfaces
• Even though primitives might apply well into Versal, their connectivity might not directly map
• UltraScale-based designs do not have embedded processors, but Versal has a processor subsystem to consider, even if you don’t intend to use it

PCB Class III and Pin Density Issues

Versal delivers increased functionality within the same footprint, but this requires higher pin density. While tighter pin pitch allows for more signals in a compact space, it also complicates routing, PCB layout optimization, and Class III PCB compliance. This is particularly challenging in VPX form factors, driven by the Department of Defense’s pursuit of open architecture in military platforms. Consider:

• Tighter pin pitches often require vias to transition signals to another layer – a complex process given Class III clearance standards
• Optimal signal integrity depends on the use of specific pad and anti-pad sizes. In some cases, designers must accept signal integrity trade-offs to meet Class III standards
• Denser packages make it challenging to comply with Class III spacing rules, increasing the risk of reliability issues
• Class III outlines strict drill-to-pad size ratios and maximum drill offsets. If a drill is offset too far, it might not maintain a strong connection, leading to potential failures in the field
• Even if it passes initial testing, an undersized connection could fail over time due to strain or overcurrent or be degraded with crosstalk and unexpected signal coupling

Ultimately, these factors might require design workarounds such as adding redrivers, reconfiguring signal routing, or even full PCB redesigns.

Power Consumption

Versal devices have more gates and smaller gate sizes than UltraScale/UltraScale+. Since static power is generated by leakage when a gate is on or off – and the smaller the gate, the greater the leakage – Versal consumes more static power.

Versals can also consume more dynamic power due to gates switching on and off. However, improvements in size, weight, and power (SWaP) enable Versal ASoCs to deliver more total work with less power consumption than UltraScale/UltraScale+.

For example, while an UltraScale/UltraScale+ might perform a function using 1W, a Versal device could perform two functions at 1.5W. Despite its higher power demand, in this hypothetical scenario Versal would achieve a more favorable power-to-work ratio (0.75W) compared to UltraScale/UltraScale+ (1W).

Engineering the Jump to Versal

Migrating from UltraScale/UltraScale+ to Versal promises enhanced performance and capabilities, but you can’t simply swap one for the other. Success depends on navigating technical challenges such as code portability, power consumption, and pin density. By understanding these hurdles upfront and planning accordingly, engineers can streamline the migration process and unlock Versal’s advanced architecture.

Have questions about Versal migration challenges? New Wave Design offers the engineering expertise to help you address them with confidence. Contact our team to start the conversation.