How Vivado™ Design Suite Supports FPGA Development and ASoC Design

AMD’s Versal™ adaptive SoC (ASoC) family offers heterogeneous acceleration and hard IP integration for industry-leading performance. But how do you reduce risk and ensure optimal results when migrating designs from past generation FPGA families, such as Ultrascale or Ultrascale+?

This blog series will present best practices used to de-risk the transition to the Versal family.

Why the Vivado™ Design Suite Matters for FPGA and ASoC Development

Before we get into the details of how to successfully migrate from Xilinx Ultrascale to AMD Versal ASoC technology, let’s first understand what AMD’s Vivado™ Design Suite is designed to do and how it streamlines risk reduction when migrating to Versal ASoC.

• Vivado is the platform for developing and implementing hardware designs on AMD’s adaptive SoCs (System-on-Chips) and FPGAs (Field-Programmable Gate Arrays).
• It’s a comprehensive, integrated development environment (IDE) that covers the entire design flow, from design entry to synthesis, place and route, verification, and simulation.
• Vivado was a ground-up rewrite of the design flow compared to its predecessor, Xilinx ISE, to address the increasing complexity and size of modern AMD (formerly Xilinx) devices.
• It provides a cohesive platform where all aspects of the hardware design process, including design, simulation, debugging, and implementation, can occur in one software suite.

Further, Vivado is designed to handle the complexity of SoC development, particularly for devices like the AMD Versal, Zynq UltraScale+, and 7 series. These devices integrate various components like hardened processors, high-speed I/O, and advanced memory interfaces, making a truly heterogeneous processing solution. It heavily promotes the use of Intellectual Property (IP) cores, both pre-built and custom, to accelerate design and facilitate reuse.

Key Features of the Vivado™ Design Suite

Perhaps most importantly, Vivado offers enhanced productivity and automation to the RTL team when developing new firmware stacks for use on ASoC hardware.

• The entire Vivado Design Suite is built on a powerful Tcl (Tool Command Language) scripting interface. Every GUI action has a corresponding Tcl command, allowing for extensive automation, customization of design flows, and repeatable builds. This is a huge advantage for advanced users and large teams.
• The Dynamic Function eXchange (DFX) feature allows for partial reconfiguration of the FPGA, enabling dynamic loading and unloading of different functionalities while the rest of the system continues to operate. This is crucial for adaptive systems and optimizing resource usage. Finally, “ChipScope” and other integrated debugging tools are more powerful and provide greater visibility into the running hardware.

These features make the Vivado™ Design Suite a stronger foundation for efficiency and adaptability in ASOC design and FPGA development.

Supporting Risk-Free FPGA Design Migration

The Vivado™ Design Suite is AMD’s most advanced software platform for developing and implementing designs on the latest ASoCs and FPGAs. It is designed to address the complexities of SoC development by generating efficiencies and automation through its integrated development environment and Tcl, DFX, and debugging features.

New Wave Design implements Vivado™ Design Suite for development of its latest FPGA-based processing solutions, such as our high speed serial interface IP cores running on our Versal-based 3U VPX FPGA modules. To learn more, contact us today.